1. Field of the Invention
This invention relates to bipolar transistors, and more particularly to SOI (semiconductor-on-insulator) bipolar transistors and associated operating methods that provide for a precise control over the active base charge.
2. Description of the Related Art
A typical conventional bipolar transistor is illustrated in FIG. 1. It consists of emitter, base and collector regions 2, 4 and 6, respectively, implanted into a semiconductor substrate 8 such as silicon, with highly doped base and collector contact implants 10 and 12. An npn device is illustrated, but the following discussion also applies to pnp devices.
During operation, the p-n emitter-base and collector-base junctions are surrounded by respective depletion regions 14 and 16, whose widths are dependent upon the bias voltages across the junctions and the doping densities on either side of the junctions. The collector-base depletion region 16 normally supports the majority of the voltage across the transistor, with the emitter-collector current flowing generally as indicated by arrow 18. This depletion region experiences large variations in the bias voltage differential developed across it. Since both the collector and base regions of the transistor are normally relatively lightly doped, they undergo large variations in the incursion of the collector-base depletion region in response to variations in collector-base voltage typical of normal transistor operation. As the depletion region expands into the base region during an increase in the collector-base voltage, the width of the base region will shrink correspondingly. The base region is relatively narrow to begin with, so that such variations in the width of the depletion layer result in large variations in the amount of available base charge.
Because the collector current is inversely proportional to the amount of base charge, this modulation of the transistor's base charge has an important effect on the device's output characteristics. These characteristics include the transistor's current gain .beta., its early voltage V.sub.A and its punchthrough breakdown voltage. In general, an increase in the base charge will reduce .beta. (normally undesirable), increase V.sub.A (normally desirable) and increase the punchthrough breakdown voltage (normally desirable). The development of a device with suitable performance for a specific application requires that the base charge be adjusted to give an optimum tradeoff between the various device parameters that depend upon the base charge. This typically requires that a less than optimum level be accepted for each individual parameter.
A transistor structure that is of interest for the present invention uses a silicon-on-insulator-on-silicon (SOIS) arrangement in which the transistor is fabricated in a silicon film, with an insulating oxide layer on the bottom; the oxide layer is in turn provided on the upper surface of an underlying silicon substrate. The dielectric oxide isolation eliminates a parasitic pnp transistor that can otherwise interfere with the desired transistor operation. However, the device still suffers from a dependence of the base charge upon the collector-base bias, as described above. This type of device is described in Ifstrom et al., "A 150-V Multiple Up-Drain VDMOS, CMOS, and Bipolar Process in `Direct Bonded` Silicon on Insulator on Silicon", IEEE Electron Device Letters, Vol 13, No 9, September 1992, pages 460-461.
A "hybrid" bipolar/MOS transistor that also uses an SOIS structure is disclosed in Parke et al., "Deep Sub-Micron, Bipolar-MOS Hybrid Transistors Fabricated on SIMOX," IEEE SOI Conference, 1992. A surface MOS device is designed so that it can support lateral bipolar transistor operation, with the surface MOS gate and the lateral bipolar base connected together. While this device has promising characteristics, there is again no disclosure of a way to prevent the base charge from varying with the collector/drain-base/gate voltage.